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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The open ISA philosophy and the standardisation landscape managed by RISC-V International
- Mental Model of RISC-V: Load-Store architecture, register file structure, and byte ordering
- Comparative analysis with ARM, x86, and POWER architectures, evaluating trade-offs for heterogeneous computing environments
- Assessment of ecosystem maturity, featuring SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standardised interfaces: RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specification covering CSR maps, exception handling, and memory hierarchies
- RV32I / RV64I instruction sets and Application Binary Interface (ABI) compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions essential for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer instructions (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Bitness-aware programming strategies tailored for 32-bit and 64-bit RISC-V targets
- Calling conventions and stack frame management critical for embedded and real-time software systems
Compiler Toolchain Proficiency
- LLVM-based compiler toolchains: utilising Clang, LLVM, and Binutils for RISC-V cross-compilation
- Linker scripts, sections, and memory layout configuration for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimisation levels, and profiling-driven code tuning
- Workflows for open-source toolchain development: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: leveraging zero-cost abstractions, unsafe memory management, and bare-metal development techniques
- No-Std environments involving custom linkers, device driver development, and memory-mapped I/O
- Development of BSPs for Zephyr RTOS and Buildroot tailored to RISC-V targets
- Peripheral interfacing: programming GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Clock gating, power domain management, and optimisation of low-power modes
- Cycle-accurate performance analysis using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency for safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI implementation of the SBI specification: bootloader firmware development
- UEFI/EDK II on RISC-V: developing modern firmware boot stacks
- Porting Coreboot and U-Boot for RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: device tree overlays, CPU topology, and interrupt controller (AIA) driver development
- Vendor BSP development and kernel configuration for custom SoC platforms
- Supporting file systems, networking stacks, and containerisation tools like Docker and Kubernetes on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IP: OpenCores, ChIPS Framework, and vendor RTL components
- Bus matrix design and memory controller integration (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesis and implementation of RISC-V cores on FPGA (e.g., BOOM, VexRiscv, PULP)
- Functional verification methodologies using SystemVerilog Assertions (SVA) and UVM
- Using formal verification tools and property-based testing for RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Vector load/store operations, vector-fused multiply-add (VFMA), and acceleration for matrix computations
- Variable-length vector operations (VL, VLEN) enabling workload-optimized SIMD execution
- Vector mask operations, segment control, and data type flexibility supporting DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators through custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends for custom instruction generation and code emission
- Strategies for hardware-software partitioning to integrate accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Neural Processing Unit architectures: systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Model quantisation techniques (INT8, INT4, FP8) suitable for edge deployment on RISC-V
- Framework compatibility including TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs with AI accelerator NPUs for real-time inference pipelines
- Memory subsystem optimisation: managing HBM/DDR bandwidth for ML model weights and activations
- Thermal and power budgeting considerations for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Security mechanisms involving Physical Memory Protection (PMP) and Page Table walkers
- Secure Enclave/TEE architectures for RISC-V: integrating OP-TEE and SEV-class trusted execution environments
- Boot chain security: establishing root of trust, secure boot, and measured launch attestation
Cryptographic Acceleration
- RISC-V cryptographic extensions (Zk, Zkr, K): accelerating SHA, AES, RSA, RSA-PSS, and ECC
- Integrating post-quantum cryptography (PQC) for next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design methodology: encoding, encoding tables, ABI impact analysis, and the RISC-V International specification submission process
- Designing custom register files with CBAR (Custom Base Address Registers) for operand dispatch
- Instruction pipelining, hazard detection, and pipeline modifications required for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Testbench design for custom extensions: generating directed versus constraint-random stimuli
- Regression testing frameworks and coverage-driven verification for architectural modifications
- Interoperability testing to ensure custom instructions function within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Ensuring ISO 26262 functional safety compliance for RISC-V automotive processors
- Establishing ASIL-Q classification and developing safety manuals for RISC-V silicon IP
- Implementing deterministic interrupt handling, lockstep core pairs, and memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Achieving IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways using RISC-V: enabling connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: designing ISA extensions and core configuration for a defined use case
- RTL implementation in SystemVerilog incorporating UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and bare-metal driver stack integration
- Customising Linux BSP and toolchains for the custom RISC-V core
- Deploying AI workloads: integrating NPUs, performing model quantisation, and benchmarking performance
- Security validation: enforcing PMP, secure boot, and benchmarking cryptographic acceleration
- Producing technical architecture documentation, analysing IP strategy, and presenting to cross-functional teams
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
